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  july 2014 docid024325 rev 2 1 / 15 this is information on a product in full production. www.st.com STL33N60M2 n - channel 600 v, 0.115 typ., 22 a mdmesh? m2 power mosfet in a powerflat? 8x8 hv package datasheet - production data figure 1 : internal schematic diagram features order code v ds @ t jmax r ds(on)max i d STL33N60M2 650 v 0.135 ? 22 a ? extremely low gate charge ? excellent output capacitance (coss) profile ? 100% avalanche tested ? zener - protected applications ? switching applications description this device is an n - channel power mosfet developed using the mdmesh? m2 technology. thanks to the strip layout associated to an improved vertical structure, the device exhibits both low o n - resistance and optimized switching characteristics. it is therefore suitable for the most demanding high efficiency converters. table 1: device summary order code marking package packaging STL33N60M2 33n60m2 powerflat? 8x8 hv tape and reel d(3) g(1) s(2) am01476v6
contents STL33N60M2 2 / 15 docid024325 rev 2 contents 1 electrical ratings ................................ ................................ ............. 3 2 electrical char acteristics ................................ ................................ 4 2.1 electrical characteristics (curves) ................................ ...................... 6 3 test circuits ................................ ................................ ..................... 8 4 package mechanical data ................................ ............................... 9 4.1 powerflat? 8x8 hv package mechanical data ........................... 10 5 packaging mechanical data ................................ .......................... 12 5.1 powerflat? 8x8 hv packaging mechanical data ......................... 12 6 revision history ................................ ................................ ............ 14
STL33N60M2 electrical ratings docid024325 rev 2 3 / 15 1 electrical ratings table 2: absolute maximum ratings symbol parameter value unit v gs gate - source voltage 25 v i d (1) drain current (continuous) at t c = 25 c 22 a i d (1) drain current (continuous) at t c = 100 c 13.8 a i dm (1) (2) drain current (pulsed) 88 a p tot (1) total dissipation a t t c = 25 c 190 w i ar avalanche current, repetitive or not - repetitive (pulse width limited by t j max) 4 a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 1100 mj dv/dt (3) peak diode recov ery voltage slope 15 v/ns dv/dt (4) mosfet dv/dt ruggedness 50 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature 150 c notes: (1) the value is rated according to r thj - case and limited by package. (2) pulse width limited by safe operating area. (3) i sd 22 a, di/dt 400 a/s, v ds(peak) < v (br)dss , vdd = 400 v. (4) v ds 480 v. table 3: thermal data symbol parameter value unit r thj - case thermal resistance junction - case max 0.66 c/w r thj - amb (1) thermal resistance j unction - ambient max 45 c/w notes: (1) when mounted on fr - 4 board of inch2, 2oz cu.
electrical characteristics STL33N60M2 4 / 15 docid024325 rev 2 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4: on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain - source breakdown voltage v gs = 0, i d = 1 ma 600 v i dss zero gate voltage drain current v gs = 0, v ds = 600 v 1 a v gs = 0, v ds = 600 v, t c =125 c 100 a i gss gate - body leakage current v ds = 0, v gs = 25 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 2 3 4 v r ds(on) static drain - source on - resistance v gs = 10 v, i d = 11 a 0.115 0.135 ? table 5: dynamic symbol parameter test conditions min . typ. max. unit c iss input capacitance v ds = 100 v, f = 1 mhz, v gs = 0 - 1781 - pf c oss output capacitance - 85 - pf c rss reverse transfer capacitance - 2.5 - pf c oss eq. (1) equivalent output capacitance v ds = 0 to 480 v, v gs = 0 - 135 - pf r g intrinsic gate resistance f = 1 mhz open drain - 5.2 - ? q g total gate charge v dd = 480 v, i d = 26 a v gs = 10 v (see figure 15: "gate charge test circuit" ) - 45.5 - nc q gs gate - source charge - 9.9 - nc q gd gate - drain charge - 18.5 - nc notes: (1) coss eq. is defined as a constant equivalent capacitance giving the same charging time as coss when vds increases from 0 to 80% vdss.
STL33N60M2 electrical characteristics docid024325 rev 2 5 / 15 table 6: switching times symbol parameter test conditions min. typ. max. unit t d(on) turn - on delay time v dd = 300 v, i d = 13 a r g = 4.7 , v gs = 10 v (see figure 14: "switching times test circuit for resistive load" ) - 16 - ns t r voltage rise time - 9.6 - ns t d(off) turn - off delay time - 109 - ns t f current fall time - 9 - ns table 7: source drain diode s ymbol parameter test conditions min. typ. max. unit i sd source - drain current - 22 a i sdm (1) source - drain current (pulsed) - 88 a v sd (2) forward on voltage i sd = 26 a, v gs = 0 - 1.6 v t rr reverse recovery time i sd = 26 a, di/dt = 100 a/s v dd = 60 v (see figure 17: " unclamped inductive load test circuit" ) - 375 ns q rr reverse recovery charge - 5.6 c i rrm reverse recovery current - 30 a t rr reverse recovery time i sd = 26 a, di/dt = 100 a/s v dd = 60 v, t j = 150 c (see figure 17: " unclamped inductive load test circuit" ) - 478 ns q rr reverse recovery charge - 7.7 c i rrm reverse recovery current - 3 2.5 a notes: (1) pulse width limited by safe operating area. (2) pulsed: pulse duration = 300 s, duty cycle 1.5%.
electrical characteristics STL33N60M2 6 / 15 docid024325 rev 2 2.2 electrical characteristics (curves) figure 2 : safe operating area figure 3 : thermal impedance figure 4 : output characteristics figure 5 : transfer characteristics figure 6 : gate charge vs gate - source voltage figure 7 : static drain - source on - resistance gipg23042014 1 134m t gipg090720140852m t r ds(on) 0. 1 14 0. 1 12 0. 1 10 0 5 i d (a) ( ) 0. 1 16 v gs =10v 10 0. 1 18 0.120 20 15 0.122 gipg080720141423m t i d 60 30 0 0 4 v gs (v) 8 (a) 2 6 10 10 40 v ds =17v 50 20 i d 50 0 0 5 v ds (v) 10 (a) 15 4v 6v v gs =7, 8, 9, 10v 20 60 20 5v 40 30 10 gipg08072014 1 147m t
STL33N60M2 electrical characteristics docid024325 rev 2 7 / 15 figure 8 : capacitance variations figure 9 : normalized gate threshold v oltage vs temperature figure 10 : normalized on - resistance vs temperature figure 11 : normalized v(br)dss vs temperature figure 12 : source - drain diode forward characteristi cs figure 13 : output capacitance stored energy gipg090720140955m t r ds(on) 1.9 1.3 0.9 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 0.7 1.1 1.5 1.7 2.1 v gs =10v 2.3 v sd 0 4 i sd (a) (v) 2 10 6 8 0 0.2 0.4 0.6 t j =-50c t j =150c t j =25c 0.8 1 1.2 1.4 16 18 20 14 12 gipg090720141014m t gipg090720141001m t v (br)dss -50 0 t j (c) (norm) -25 75 25 50 100 0.91 0.93 0.99 1.03 i d =1m a 1.07 1. 1 1 0.95 0.97 1.01 1.05 1.09 gipg23042014 1 137m t gipg23042014 1 136m t gipg23042014 1 135m t
test circuits STL33N60M2 8 / 15 docid024325 rev 2 3 test circuits figure 14 : switching times test circuit for resistive load figure 15 : gate charge test circuit figure 16 : test circuit for inductive load switching and diode recovery times figure 17 : unclamped inductive load te st circuit figure 18 : unclamped inductive waveform figure 19 : switching time waveform m m w m m m m m
STL33N60M2 package mechanical data docid024325 rev 2 9 / 15 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark.
package mechanical data STL33N60M2 10 / 15 docid024325 rev 2 4.1 powerflat? 8x8 hv package mechanical data figure 20 : powerflat? 8x8 hv drawi ng mechanical data
STL33N60M2 package mechanical data docid024325 rev 2 11 / 15 table 8: powerflat? 8x8 hv mechanical data dim. mm min. typ. max. a 0.80 0.90 1.00 a1 0.00 0.02 0.05 b 0.95 1.00 1.05 d 8.00 e 8.00 d2 7.05 7.20 7.30 e2 4.15 4.30 4.40 e 2.00 l 0.40 0.50 0.60 figure 21 : powerflat? 8x8 hv recommended footprint
packaging mecha nical data STL33N60M2 12 / 15 docid024325 rev 2 5 packaging mechanical data 5.1 powerflat? 8x8 hv packaging mechanical data figure 22 : powerflat? 8x8 hv tape figure 23 : powerflat? 8x8 hv package orientation in carrier tape. w (16.000.3) e (1.750.1) f (7.500.1) a0 (8.300.1) p1 (12.000.1) p2 (2.00.1) p0 (4.00.1) d0 ( 1.550.05) d1 ( 1.5 min) t (0.300.05) b0 (8.300.1) k0 (1.100.1) note: b a s e a nd b u l k qu a n t i t y 300 0 p c s
STL33N60M2 packaging mechanical data docid024325 rev 2 13 / 15 figure 24 : powerflat? 8x8 hv reel 8229819_reel_rev a
revision history STL33N60M2 14 / 15 docid024325 rev 2 6 revision history table 9: document revision history date revision changes 26 - jun - 2013 1 first release. 23 - jul - 2014 2 updated the title, the features and the description in cover page. document status promoted from preliminary data to production data. updated figure 1: "internal schematic diagram" , section 1: "electrical ratings" , section 2: "electrical characteristics" . added section 2.1: "electrical characteristics (curves)" updated section 3: "test circuits" , section 4.1: "powerflat? 8x8 hv package mechanical data" .
STL33N60M2 docid024325 rev 2 15 / 15 important notice C please read carefully stmicroelectronics nv and its subsidiaries (st ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders . st products are sold pursuant to sts terms and conditions of sale in place at the time of order acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for applicati on assistanc e or the design of purchasers products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted b y st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions o f this document. ? 2014 stmicroelectronics C all rights reserved


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